عنوان المقالة: Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA
أ د خميس عواد زيدان | Khamis A. Zidan | 10408
نوع النشر
مجلة علمية
المؤلفون بالعربي
المؤلفون بالإنجليزي
Dr. Dhafer R. Zaghar, Khamis A. Zidan, Laiyth M. Al-Rawi
الملخص الانجليزي
There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost. The second method implements LUT as logic gates. This method requires special software and gives a low speed implies. This paper proposed a modification to the second method that will save the speed of the first method and low cost of the second method. It depends on the design of the LUT. Therefore it will not require special software.
تاريخ النشر
03/06/2005
الناشر
Journal of Engineering and Sustainable Development (JEASD)
رقم المجلد
9
رقم العدد
2
رابط خارجي
https://www.iasj.net/iasj/article/10082
الكلمات المفتاحية
Xilinx chip
رجوع