عنوان المقالة:نواة FPGA لتسريع فك ترميز رمازات QR FPGA Hardware Implementation for Accelerating QR Decoding
محمد الحمامي | Muhammad Alhammami | 8092
Publication Type
Journal
Arabic Authors
د. محمّد الحمّامي وآخرون
English Authors
Muhammad Alhammamia , Chee Pun Ooia , Wooi-Haw Tana and Soon Nyeancheonga
Abstract
نواة FPGA لتسريع فك ترميز رمازات QR
Abstract
QR codes has gained more attention as an input interface to many embedded applications. However, some applications need extra computing resources which demand high-performance QR code decoder. This study suggests a hardware solution to accelerate the decoding function. The proposed design is implemented using CYCLON II FPGA from Altera with the decoded results display on a LCD. The initial experiments show that it is possible to decode the unmasked QR raw bits efficiently in real time which shows good potential to offload the computationally intensive task of QR image decoding process from the main processor and to room for advanced image pre-processing and security decryption algorithm to be implemented in FPGA.
Publication Date
12/1/2016
Publisher
Journal of Engineering and Applied Sciences
Volume No
11
Issue No
14
ISSN/ISBN
1818-7803
DOI
10.3923/jeasci.2016.3273.3278
Pages
3273-3278
External Link
http://www.medwelljournals.com/abstract/?doi=jeasci.2016.3273.3278
Keywords
QR code, QR decoding, FPGA, Hardware implementation, high performance
رجوع