عنوان المقالة:ADOPTING SYSTEMATIC QUALITY SIGNING AND VERIFICATION PROCESSES FOR SEQUENTIAL HARDWARE TESTING ADOPTING SYSTEMATIC QUALITY SIGNING AND VERIFICATION PROCESSES FOR SEQUENTIAL HARDWARE TESTING
محمد عصام يونس . كمال زهيري زاملي, نور اشيدي مات عيسى
English Authors
Mohammed I. Younis, Kamal Z. Zamli, N. A. Mat Isa
Abstract
This paper discusses an improvement of the strategy for Quality Signing and Verification Processes. Earlier studies demonstrate that the strategy relies on two processes: Quality Signing Process and Quality Verification Process, respectively. The Quality Signing Process is based on integration of black box (i.e. Combinatorial Interaction Testing) and white box (i.e. Mutation Testing) techniques in order to derive an optimum test suite for the Quality Verification Process. In this case, the generated test suite significantly improves the Quality Verification Process. Unlike the previous work, which deals only with combinatorial logic, an improvement of the strategy now addresses sequential logic, that is, by incorporating both the state of the system as well as the input parameter values as input in both processes. As a case study, this paper describes the step-by-step application of the strategy for testing a 12-bit Linear Feedback Shift Register in a hardware production line. The result demonstrates that the proposed strategy gives saving effort factor of 99.7%. Additionally, the result also demonstrates the need to consider Combinatorial Interaction Testing in both cumulative and normal mode of operation.
Abstract
This paper discusses an improvement of the strategy for Quality Signing and Verification Processes. Earlier studies demonstrate that the strategy relies on two processes: Quality Signing Process and Quality Verification Process, respectively. The Quality Signing Process is based on integration of black box (i.e. Combinatorial Interaction Testing) and white box (i.e. Mutation Testing) techniques in order to derive an optimum test suite for the Quality Verification Process. In this case, the generated test suite significantly improves the Quality Verification Process. Unlike the previous work, which deals only with combinatorial logic, an improvement of the strategy now addresses sequential logic, that is, by incorporating both the state of the system as well as the input parameter values as input in both processes. As a case study, this paper describes the step-by-step application of the strategy for testing a 12-bit Linear Feedback Shift Register in a hardware production line. The result demonstrates that the proposed strategy gives saving effort factor of 99.7%. Additionally, the result also demonstrates the need to consider Combinatorial Interaction Testing in both cumulative and normal mode of operation.
ا.د. محمد عصام يونس | Mohammed I. Younis | 13043